APEmille ASSEMBLER

The APEmille assembly language is completely new. All the assembler instructions can be executed on the hardware devices without any macro expansion. The assembly language supports full relocatability. A Zz-based translator from Ape100 Assembler into APEmilleAssembler is already available.

The assembler codes are the following:

Arithmetic instructions

TADD reg reg reg

TSUB reg reg reg

TMUL reg reg reg

TDIV reg reg reg

TMULA reg reg reg

TADD3 reg reg reg reg

TAGU1 reg MOP1

TAGU2 reg MOP2

TAGU3 reg MOP3

Bitwise instructions

TAND reg reg reg

TOR reg reg reg

TXOR reg reg reg

TNAND reg reg reg

TNOR reg reg reg

TXNOR reg reg reg

TASH reg reg reg

TLSH reg reg reg

TROT reg reg reg

Data transfer instructions

MEMTOT1 reg[:n] MOP

1 MEMTOT2 reg[:n] MOP2

MEMTOT3 reg[:n] MOP3

TTOMEM1 MOP1 reg[:n]

TTOMEM2 MOP2 reg[:n]

TTOMEM3 MOP3 reg[:n]

Flow control instructions

TEQ reg reg

TNE reg reg

TGT reg reg

TLT reg reg

TGE reg reg

TLE reg reg

TINCCOMP reg reg reg

TANY

TNONE

TCNB

TGETPC reg

TLOADSR reg

TSTORESR reg

JUMP reg lab

JUMPIF reg lab

JUMPIFNOT reg lab

LABEL lab

HALT

TCONST adr [slice] const

TCHAR adr [slice] string

Jmille instructions

Single precision arithmetics

JSNORM_PP reg reg reg reg

JSNORM_PM reg reg reg reg

JSNORM_MP reg reg reg reg

JSNORM_MM reg reg reg reg

JSNORMABS_PP reg reg reg reg

JSNORMABS_PM reg reg reg reg

JSNORMABS_MP reg reg reg reg

JSNORMABS_MM reg reg reg reg

JSADD3_PPP reg reg reg reg

JSADD3_PPM reg reg reg reg

JSADD3_PMP reg reg reg reg

JSADD3_PMM reg reg reg reg

JSADD3_MPP reg reg reg reg

JSADD3_MPM reg reg reg reg

JSADD3_MMP reg reg reg reg

JSADD3_MMM reg reg reg reg

Complex single precision arithmetics

JCNORM_PP reg reg reg reg

JCNORM_PM reg reg reg reg

JCNORM_MP reg reg reg reg

JCNORM_MM reg reg reg reg

JCNORMABS_PP reg reg reg reg

JCNORMABS_PM reg reg reg reg

JCNORMABS_MP reg reg reg reg

JCNORMABS_MM reg reg reg reg

Double precision arithmetics

JDNORM_PP reg reg reg reg

JDNORM_PM reg reg reg reg

JDNORM_MP reg reg reg reg

JDNORM_MM reg reg reg reg

JDNORMABS_PP reg reg reg reg

JDNORMABS_PM reg reg reg reg

JDNORMABS_MP reg reg reg reg

JDNORMABS_MM reg reg reg reg

Local integer arithmetics

JINORM_P reg reg reg reg

JINORM_M reg reg reg reg

Jmille logic and bitwise operations

JIAND reg reg reg

JINAND reg reg reg

JIOR reg reg reg

JIXOR reg reg reg

JILSH reg reg

JIASH reg reg

JIROT reg reg

Look Up Table instructions

JEXP reg reg

JINV reg reg

JINVSQRT reg reg

JLOGE reg reg

JLOGM reg reg

JLSB reg reg

JLUTNOP reg reg

Local boolean conditions and IF stack

JSPUSHEQ reg reg

JSPUSHNE reg reg

JSPUSHGT reg reg

JSPUSHLT reg reg

JSPUSHGE reg reg

JSPUSHLE reg reg

JCPUSHEQ reg reg

JCPUSHNE reg reg

JDPUSHEQ reg reg

JDPUSHNE reg reg

JDPUSHGT reg reg

JDPUSHLT reg reg

JDPUSHGE reg reg

JDPUSHLE reg reg

JIPUSHEQ reg reg

JIPUSHNE reg reg

JIPUSHGT reg reg

JIPUSHLT reg reg

JIPUSHGE reg reg

JIPUSHLE reg reg

JPOP

JSTKAND

JSTKOR

JSTKNOT

JSTKXOR

JSTKRESET

Type conversion instructions

JSTOD reg reg

JSTOI reg reg

JDTOS reg reg

JDTOI reg reg

JITOS reg reg

JITOD reg reg

JSTKTOI reg

Data transfer instructions

JTOMEM1 MOP1 [LOF] reg[:n]

MEMTOJ1 reg[:n] MOP1 [LOF]

JTOMEM2 MOP2 [LOF] reg[:n]

MEMTOJ2 reg[:n] MOP2 [LOF]

JTOMEM3 MOP3 [LOF] reg[:n]

MEMTOJ4 reg[:n] MOP3 [LOF]

JCONST adr [slice] const [const]

JCHAR adr [slice] string

JGETSR reg

JPUTSR reg

Data transfer among chips

JTOC0 reg

JTOC1 reg

JTOC2 reg

JSEND MOP[:n] [LOF]

JREC reg[:n]

CTOT reg

TTOJ1 reg MOP1

TTOJ2 reg MOP2

TTOJ3 reg MOP3

Software exceptions

JEX TEX