MEMORIES

All the APEmille memories should be capable to work in the frequency range from a minimum 66MHz up to the maximum frequency, 100MHz. Moreover it should be possible to use APEmille in single cycle (in a step-by-step mode) for debugging purpose. A balanced machine architecture (for QCD, ...) requires one access to the floating point data memory every 8 floating point operations. Jmille is able to perform 8 flops every clock cycle in complex operations. For this reason it should be able to perform one memory access for each cycle.

• Technology
• Processing Board Memories
  

 Memory technology

Two tecnologies will be used for the different memories:

1. SDRAM 16Mbit CMOS technology:

Access time: 10ns (100 MHz)

Easily available organization: 2Mx8 (2x1Mx8) and 1Mx16 (2x512kx16)

2. Cache-SRAM or SynchronousSRAM technology:

Access time: < 10ns (>100 MHz)

Easily available organization: 32Kx32 or 64kx16

 Processing Board Memories

APEmille will use four memory sets, (replaced on each processing board) dedicated to Jmille and Tmille data and program memory.

• Jmille data memory - 40 bits

type: SDRAM

organization 2Mx8: 2 MW-> 5 chips required per FPU node (2000 nodes: 10000 chips)

• Jmille program memory - 80 bits (two different banks of 80 bit at half frequency or one bank of 80 bits full frequency)

type: SDRAM

organization 2x512Kx16: 512KW-> 10chips / 5 chips (256 boards: 2560 chips / 1280 )

• Tmille program memory - 96 bits

type: SDRAM

organization 2x512Kx16: 512KW->6 chips (256 boards: 1550 chips)

• Tmille data memory - 40 bits

type: SynchronousSRAM

organization 32Kx32: 128KW->8 chips (256 boards: 2048 chips)

alternative: 64Kx16 128KW->6 chips (256 boards: 1550 chips)

• Total chips used for 256 boards (APEmille 4 towers):

minimum: 14380

maximum: 16158